Senior Manager, ASIC Design - San Jose California

Company: Conductor
Location: San Jose, California
Posted On: 01/18/2025

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.Advancing the World's Technology TogetherOur technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll DoThe Senior Manager, ASIC Design involves working on cutting edge ASIC's in advanced nodes involving Monolithic / 2.5D / 3D / Chiplet based designs. The candidate will be working with external customers and internal teams and manage the end to end design implementation from spec to silicon, chip-level floorplan, budgeting and partitioning, 2.5D interposer planning, 3DIC early thermal analysis, chiplet planning and integration.Location: Onsite at our San Jose headquarters 5 days a week with an average of 15-20% travel per year.Reports to: Senior Director, ASIC EngineeringJob ID: 42337

• Solid experience in full chip prototype solution, memory selection, die size estimation, trade off analysis monolithic vs 2.5D vs chiplet based designs
• Solid understanding of DFT strategies, streaming scan fabric, 1838 protocol
• Solid experience in high speed CTS, timing closure on highly complex SoC
• Solid experience in using place and route tools and achieving the best PPA of the full-chip physical design
• Solid experience with advanced nodes like 3, 4, 5, 7 nm
• Solid knowledge of NOC (Network on Chip from Netspeed / Arteris) Physical Implementation
• Solid experience of writing timing constraints, integrating IP constraints and working closely with STA and logic design engineers to close timing
• Solid experience in PDN build and power integrity analysis flow (static/dynamic IR-drop analysis)
• Solid experience in EM analysis and fix
• Solid experience in physical verification flow including DRC, LVS, PERC and DFM rule checking and fix
• Solid experience in project management ASIC with good understanding of RTL, Synthesis, DFT, Design Verification, Physical Design, STA, Physical Verification, Package, Co-Package Optics, Test, Assembly, Silicon Bring up etc
• Customer technical interaction, memory selection, IP Integration discussions with design team.
• Project Management of ASIC's.
• Complete other responsibilities as assigned.What You Bring
  • Bachelors in Electrical Engineering or related Physical Science with 20+ years of experience or Masters in Electrical Engineering or related Physical Science with 18+ Years of Industry Experience or PhD in Electrical Engineering or related Physical Science with 15+ years of experience.
  • Direct experience in ASIC or chip design, with significant hands on experience in large complex projects involving HPC (AI / ML / Bufferless HBM /) Monolithic, 2.5D / 3D / Chiplet based designs.
  • Strong Knowledge in hierarchical physical design methodologies, chip floorplan, building on-chip PDN, partitioning, place-and-route, IR-drop analysis, EM analysis and physical verification, package Co-Optics.
  • Comfortable working with internal and managing 3rd party teams.
  • Highly passionate and energetic.
  • You're inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.What We OfferThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors-including the role's function and location, as well as the individual's knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance.This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.Base Pay Range$180,950 - $289,050 USDEqual Opportunity Employment PolicySamsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.Covid-19 PolicyTo help keep our employees, customers, and communities safe, we've developed guidelines for our teams. Currently, we encourage vaccination for all employees and may require it depending on job functions (e.g., traveling for business, meeting with customers). While visiting our offices or attending team events, we ask employees to complete a daily health questionnaire and complete a weekly COVID test. Our COVID policies are subject to change depending on public health, regulatory and business circumstances.Applicant Privacy Policyhttps://semiconductor.samsung.com/us/careers/privacy
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