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Director, Digital Design Verification - Santa Clara California
Company: Fabric of Truth, Inc Location: Santa Clara, California
Posted On: 01/23/2025
FABRIC CRYPTOGRAPHYFABRIC CREATES NEXT-GENERATION CRYPTOGRAPHY TECHNOLOGY THAT REIMAGINES TRUST AND PRIVACY.Fabric is a fast-growing Series A full-stack silicon, hardware and cloud company that was founded to unlock the next generation of cryptography. Encryption and decryption secured the Internet as we know it. The next paradigm of cryptography is revolutionizing how we trust each other.We are the first to build a new class of processor for the rapidly emerging verifiable compute market. Fabric's flagship product - the Verifiable Processing Unit (VPU) is a general-purpose, fully programmable cryptography chip built from the ground up to accelerate next-gen cryptography, such as zero-knowledge proofs and fully homomorphic encryption. With $39 million in equity and > $50 million in pre-orders, we are rapidly scaling our team of 60+ employees to build the foundation of verifiability for the Internet.About the jobWe are seeking an experienced Director of Design Verification to lead our design verification team. In partnership with our design team, this individual will be responsible for overseeing the verification of our innovative VPU and ensuring the delivery of high-quality, bug-free silicon. The ideal candidate will possess a strong background in electrical engineering, extensive experience in design verification, and a proven track record in the industry.What you'll be doing... - Reporting to our VP of Hardware Eng., lead and manage the design verification team to ensure the delivery of high-quality, bug-free silicon.
- Develop and implement advanced test-bench environments and design verification processes.
- Collaborate with cross-functional teams, including design, architecture, and software, to ensure comprehensive verification coverage.
- Develop and execute verification plans, including block-level and system-on-chip (SOC) level testbenches.
- Utilize SystemVerilog and UVM for the development of sophisticated verification environments.
- Apply randomly constrained testing methodologies to thoroughly verify complex designs.
- Employ formal verification flow and tools to ensure design correctness.
- Develop and maintain Python and/or Perl scripts to support verification activities.
- Ensure thorough documentation and clear communication of verification concepts and results to stakeholders.Qualifications and experience requirements...
- Bachelor's degree in electrical engineering or related fields; advanced degrees (MS, PhD) are a plus.
- 15-20+ years of design verification experience, with a strong background in building testbench environments and developing design verification processes. 5-10 years of experience managing/leading/building teams.
- Excellent verbal and written communication skills, with the ability to clearly communicate complex concepts to stakeholders.
- Extensive experience in building block, CPU, and SOC testbench development.
- Proficient in SystemVerilog and UVM.
- Strong understanding of randomly constrained testing methodologies.
- Experience with formal verification flow and tools.
- Proficiency in Python.
- In-depth knowledge of ASIC design flow.
- Experience with silicon bring-up, debug, and manufacturing ATE support.
- Proven track record of delivering high-quality, bug-free silicon.
- Familiarity with emulators, development boards and systems, or system simulators and software integrated verification efforts is a plus.Why Fabric?Our benefits are here to support you!
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