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ASIC Verification Engineer - San Jose California
Company: Cisco Systems, Inc. Location: San Jose, California
Posted On: 01/27/2025
Application window has been extended and expected to close on 01/27/2025. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With -2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. You will work with front-end RTL Design and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as part of ASIC development to create a flawless handshake between hardware and software functionalities and qualify use-case requirements. You'll also have the opportunity to work with systems-testing teams during post-silicon validation efforts to bring-up, debug and qualify the ASIC in deployment-mode applications. Your Impact You will participate in the ASIC design verification for Cisco high-end switching Products, one of the largest and most sophisticated of its kind in the industry. You will use the microarchitecture and define the verification plan and be responsible for the entire verification process. You will develop the verification environment, including creating and executing test plans, and perform any necessary debugging. You will take part in the development of simulation models, test plan, code or functional coverage, multi-chip/system simulation, and performance analysis. Minimum Qualifications: - BSEE/CS combined with 4+ years of related experience.
- 4+ Years post graduate hands on experience with System Verilog / UVM programming
- 4+ Years post graduate ASIC Verification processes, methodologies, flows and tools
- Experience with scripting languages Python or Perl
- Previous experience in debugging
- Experience working on Linux / Unix Preferred Qualifications:
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