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Senior ASIC Design Engineer - San Jose California
Company: Cisco Systems, Inc. Location: San Jose, California
Posted On: 02/06/2025
The application window is expected to close on 2/10/2024. This is an onsite position located in San Jose, CA.Meet the TeamJoin the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf--, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.Your Impact - Write micro-architecture specifications and participate in reviews.
- Implement Verilog RTL to meet timing, performance, and power requirements.
- Contribute to full chip integration and timing methodology/analysis.
- Develop and analyze functional coverage.
- Help define, evolve, and support our design methodology.
- Collaborate with the verification team to address design bugs and close code coverage.
- Work closely with the physical design team to close design timing and place-and-route issues.
- Triage, debug, and root cause simulation, software bring-up, and customer failures.
- Perform diagnostic and post-silicon validation tests in the lab.Minimum Qualifications:
- Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+ years of ASIC design experience.
- Prior experience working with Verilog or System Verilog programming skills.
- Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime).
- Experience with debugging and verification methodologies.Preferred Qualifications:
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